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[AK4397]
AK4397
High Performance Premium 32-Bit DAC
GENERAL DESCRIPTION The AK4397 is a high performance premium 32bit DAC for the 192kHz sampling mode of DVD-Audio including a 32bit digital filter. Using AKM's multi bit architecture for its modulator the AK4397 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4397 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4397 accepts 192kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including DVD-Audio and SACD. The AK4397 has a functional compatibility with the AK4393/4/5 and lower power dissipation. FEATURES * 128x Over sampling * Sampling Rate: 30kHz 216kHz * 32Bit 8x Digital Filter (Slow-roll-off option) Ripple: 0.005dB, Attenuation: 75dB * High Tolerance to Clock Jitter * Low Distortion Differential Output * DSD data input available * Digital De-emphasis for 32, 44.1, 48kHz sampling * Soft Mute * Digital Attenuator (Linear 256 steps) * THD+N: -103dB * DR, S/N: 120dB * I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD * Master Clock: Normal Speed: 256fs, 384fs, 512fs, 768fs or 1152fs Double Speed: 128fs, 192fs, 256fs or 384fs Quad Speed: 128fs or 192fs DSD: 512fs or 768fs * Power Supply: 4.75 5.25V * TTL Level Digital I/F * Package: 44pin LQFP
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[AK4397]
Block Diagram
DVDD VSS4 PDN SMUTE DFS0 AVDD VSS3 VDDL VSS2 VREFLH VREFLL ACKS BICK/DCLK LRCK/DSDR SDATA/DSDL DIF0/DCLK DIF1/DSDL DIF2/DSDR CAD0 CAD1 Control Register DSD Data Interface De-emphasis Control PCM Data Interface De-emphasis DATT Soft Mute De-emphasis DATT Soft Mute 8X Interpolator 8X Interpolator Modulator Modulator SCF AOUTL+ AOUTLSCF AOUTR+ AOUTRVDDR VSS1 VREFHR VREFLR
Clock Divider
CSN CCLK CDTI P/S
MCLK
DEM0 DEM1 TST1/DZFL
Block Diagram
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[AK4397]
Ordering Guide
AK4397EQ AKD4397 -10 +70C 44pin LQFP (0.8mm pitch) Evaluation Board for AK4397
Pin Layout
32
31
30
29
28
27
26
25
24
AOUTLP NC NC NC NC NC VSS3 AVDD MCLK VSS4 NC
34 35 36 37 38 39 40 41 42 43 44 10 1 4 6 9 11 3 5 7 2 8 Top View
33
23 22 21 20
AOUTRN
VREFHR
AOUTLN
VREFLR
VREFHL
VREFLL
VDDR
VDDL
VSS2
VSS1
NC
AOUTRP NC NC NC NC TST2/CAD1 TST1/DZFL ACKS/DZFR P/S NC DIF2/DSDR
AK4397EQ
19 18 17 16 15 14 13 12
SDATA/DSDL
LRCK/DSDR
SMUTE/CSN
DEM0/CCLK
DEM1/CDT1
DFS0/CAD0
BICK/DCLK
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DIF1/DSDL
DVDD
PDN
DIF0/DCLK
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[AK4397]
PIN/FUNCTION
No. 1 2 Pin Name DVDD PDN BICK DCLK SDATA DSDL LRCK DSDR SMUTE CSN DFS0 CAD0 DEM0 CCLK DEM1 CDTI DIF0 DCLK DIF1 DSDL DIF2 DSDR NC I/O I I I I I I I I I I I I I I I I I I I I I Function Digital Power Supply Pin, 4.75 5.25V Power-Down Mode Pin When at "L", the AK4397 is in power-down mode and is held in reset. The AK4397 should always be reset upon power-up. Audio Serial Data Clock Pin in PCM Mode DSD Clock Pin in DSD mode Audio Serial Data Input Pin in PCM Mode DSD Lch Data Input Pin in DSD Mode L/R Clock Pin in PCM Mode DSD Rch Data Input Pin in DSD Mode Soft Mute Pin in Parallel Mode When this pin goes "H", soft mute cycle is initiated. When returning "L", the output mute releases. Chip Select Pin in Serial Mode Sampling Speed Mode Select Pin in Parallel Mode (Internal pull-down pin) Chip Address 0 Pin in Serial Mode (Internal pull-down pin) De-emphasis Enable 0 Pin in Parallel Mode Control Data Clock Pin in Serial Mode De-emphasis Enable 1 Pin in Parallel Mode Control Data Input Pin in Serial Mode Digital Input Format 0 Pin in PCM Mode DSD Clock Pin in DSD Mode Digital Input Format 1 Pin in PCM Mode DSD Lch Data Input Pin in DSD Mode Digital Input Format 2 Pin in PCM Mode DSD Rch Data Input Pin in DSD Mode No internal bonding. Connect to GND.
3 4 5
6
7 8 9 10 11 12 13
Note: All input pins except internal pull-up/down pins should not be left floating.
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[AK4397]
Parallel/Serial Select Pin (Internal pull-up pin) "L": Serial Mode, "H": Parallel Mode ACKS I Master Clock Auto Setting Mode Pin in Parallel Mode 15 DZFR O Rch Zero Input Detect Pin in Serial Mode Test 1 Pin in Parallel Mode TST1 O Should be open. 16 DZFL O Lch Zero Input Detect Pin in Serial Mode Test 2 Pin in Parallel Mode (Internal pull-down pin) TST2 I Connect to GND. 17 CAD1 I Chip Address 1 Pin in Serial Mode (Internal pull-down pin) No internal bonding. 18 NC Connect to GND. No internal bonding. 19 NC Connect to GND. No internal bonding. 20 NC Connect to GND. No internal bonding. 21 NC Connect to GND. 22 AOUTRP O Rch Positive Analog Output Pin 23 AOUTRN O Rch Negative Analog Output Pin 24 VSS1 Ground Pin 25 VDDR Rch Analog Power Supply Pin, 4.75 5.25V 26 VREFHR I Rch High Level Voltage Reference Input Pin 27 VREFLR I Rch Low Level Voltage Reference Input Pin No internal bonding. 28 NC Connect to GND. 29 VREFLL I Lch Low Level Voltage Reference Input Pin 30 VREFHL I Lch High Level Voltage Reference Input Pin 31 VDDL Lch Analog Power Supply Pin, 4.75 5.25V 32 VSS2 Ground Pin 33 AOUTLN O Lch Negative Analog Output Pin 34 AOUTLP O Lch Positive Analog Output Pin No internal bonding. 35 NC Connect to GND. No internal bonding. 36 NC Connect to GND. No internal bonding. 37 NC Connect to GND. No internal bonding. 38 NC Connect to GND. No internal bonding. 39 NC Connect to GND. 40 VSS3 Ground Pin 41 AVDD Analog Power Supply Pin, 4.75 5.25V 42 MCLK I Master Clock Input Pin 43 VSS4 Ground Pin No internal bonding. 44 NC Connect to GND. Note: All input pins except internal pull-up/down pins should not be left floating. 14 P/S I
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[AK4397]
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. (1) Parallel Mode (PCM Mode only) Classification Analog Pin Name AOUTLP, AOUTLN AOUTRP, AOUTRN SMUTE TST1 TST2 Setting These pins should be open. These pins should be open. This pin should be connected to VSS4. This pin should be open. This pin should be connected to VSS4.
Digital
(2) Serial Mode 1. PCM Mode Classification Analog Digital Pin Name AOUTLP, AOUTLN AOUTRP, AOUTRN DIF2, DIF1, DIF0 DZFL, DZFR Setting These pins should be open. These pins should be open. These pins should be connected to VSS4. These pins should be open.
2. DSD Mode * In case of using #3(DCLK), #4(DSDL) and #5(DSDR) pins Classification Analog Digital Pin Name AOUTLP, AOUTLN AOUTR+, AOUTR- DCLK(#10), DSDL(#11), DSDR(#12) DZFL, DZFR Setting These pins should be open. These pins should be open. These pins should be connected to VSS4. These pins should be open.
* In case of using #10(DCLK), #11(DSDL) and #12(DSDR) pins Classification Analog Digital Pin Name AOUTLP, AOUTLN AOUTRP, AOUTRN DCLK(#3), DSDL(#4), DSDR(#5) DZFL, DZFR Setting These pins should be open. These pins should be open. These pins should be connected to VSS4. These pins should be open.
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[AK4397]
ABSOLUTE MAXIMUM RATINGS
(VSS1-4 = 0V; Note 1) Parameter Power Supplies: Analog Analog Digital Input Current, Any pin Except Supplies Digital Input Voltage Ambient Temperature (Power applied) Storage Temperature Symbol AVDD VDDL/R DVDD IIN VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 6.0 10 DVDD+0.3 70 150 Units V V V mA V C C
Note 1. All voltages with respect to ground. Note 2. VSS1-4 must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (VSS1-4 =0V; Note 1) Parameter Symbol min typ Analog Power Supplies: AVDD 4.75 5.0 Analog (Note 3) VDDL/R 4.75 5.0 Digital DVDD 4.75 5.0 "H" voltage reference Voltage Reference VREFHL/R AVDD-0.5 "L" voltage reference (Note 4) VREFLL/R VSS VREFH-VREFL 3.0 VREF
Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not critical. Note 4. Analog output voltage scales with the voltage of (VREFH - VREFL). AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 2.8Vppx (VREFHL/R - VREFLL/R)/5.
max 5.25 5.25 5.25 AVDD AVDD
Units V V V V V V
* AKEMD assumes no responsibility for the usage beyond the conditions in this data sheet.
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[AK4397]
ANALOG CHARACTERISTICS (Ta=25C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS; Input data=24bit; RL 1k; BICK=64fs; Input Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 18; unless otherwise specified.) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 5) 0dBFS -103 -93 dB fs=44.1kHz THD+N BW=20kHz -57 dB -60dBFS 0dBFS -100 dB fs=96kHz BW=40kHz -54 dB -60dBFS 0dBFS -100 dB fs=192kHz BW=40kHz -60dBFS -54 dB BW=80kHz -51 dB -60dBFS Dynamic Range (-60dBFS with A-weighted) (Note 6) 114 120 dB S/N (A-weighted) (Note 7) 114 120 dB Interchannel Isolation (1kHz) 100 110 dB DC Accuracy Interchannel Gain Mismatch 0.15 0.3 dB Gain Drift (Note 8) 20 ppm/C Output Voltage (Note 9) 2.65 2.8 2.95 Vpp Load Capacitance 25 pF Load Resistance (Note 10) 1 k Power Supplies Power Supply Current Normal operation (PDN pin = "H") AVDD + VDDL/R 32 47 mA 21 mA DVDD (fs 96kHz) 27 41 mA DVDD (fs = 192kHz) Power down (PDN pin = "L") (Note 11) AVDD+DVDD 10 100 A Power Supply Rejection (Note 12) 50 dB
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual. Note 6. By Figure 18. External LPF Circuit Example 2.101dB at 16bit data and 118dB at 20bit data. Note 7. By Figure 18. External LPF Circuit Example 2. S/N does not depend on input bit length. Note 8. The voltage on (VREFHL/R - VREFLL/R) is held +5V externally. Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R - VREFLL/R). AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 2.8Vpp x (VREFHL/R - VREFLL/R)/5. Note 10. Regarding Load Resistance, AC load is 1 k (min) with DC cut capacitor. Please refer to Figure 18. DC load is 1.5k (min) without DC cut capacitor. Please refer to Figure 17. Load Resistance value defines apposite to ground voltage. Analog performance is sensitive to capacitive load that is connected output pin. Therefore capacitive load must be minimized. Note 11. In the power-down mode. P/S pin = DVDD, and all other digital input pins including clock pins (MCLK, BICK and LRCK) are held VSS4. Note 12. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFHL/R pin is held +5V.
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SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bi ="0") Parameter Symbol min typ max Units Digital Filter Passband (Note 13) 0.01dB PB 0 20.0 kHz -6.0dB 22.05 kHz Stopband (Note 13) SB 24.1 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 75 dB Group Delay (Note 14) GD 28 1/fs Digital Filter + SCF Frequency Response : 0 20.0kHz 0.2 dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Double Speed Mode; DEM=OFF; SLOW bit="0") Parameter Symbol min typ max Units Digital Filter Passband (Note 13) 0.01dB PB 0 43.5 kHz -6.0dB 48.0 kHz Stopband (Note 13) SB 52.5 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 75 dB Group Delay (Note 14) GD 28 1/fs Digital Filter + SCF Frequency Response : 0 40.0kHz 0.3 dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit="0") Parameter Symbol min typ max Units Digital Filter Passband (Note 13) 0.01dB PB 0 87.0 kHz -6.0dB 96.0 kHz Stopband (Note 13) SB 105 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 75 dB Group Delay (Note 14) GD 28 1/fs Digital Filter + SCF Frequency Response : 0 80.0kHz +0/-1 dB
Note 13. The passband and stopband frequencies scale with fs. For example, PB = 0.4535xfs (@0.01dB), SB = 0.546xfs. Note 14. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal.
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[AK4397]
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit="1") Parameter Symbol min typ max Units Digital Filter Passband (Note 15) 0.04dB PB 0 8.1 kHz -3.0dB 18.2 kHz Stopband (Note 15) SB 39.2 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 72 dB Group Delay (Note 14) GD 28 1/fs Digital Filter + SCF Frequency Response: 0 20.0kHz +0/-5 dB
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; DEM=OFF; SLOW bit="1") Parameter Symbol min typ max Digital Filter Passband (Note 15) 0.04dB PB 0 17.7 -3.0dB 39.6 Stopband (Note 15) SB 85.3 Passband Ripple PR 0.005 Stopband Attenuation SA 72 Group Delay (Note 14) GD 28 Digital Filter + SCF Frequency Response: 0 40.0kHz +0/-4 -
Units kHz kHz kHz dB dB 1/fs dB
SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit="1") Parameter Symbol min typ max Units Digital Filter Passband (Note 15) 0.04dB PB 0 35.5 kHz -3.0dB 79.1 kHz Stopband (Note 15) SB 171 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 72 dB Group Delay (Note 14) GD 28 1/fs Digital Filter + SCF Frequency Response: 0 80.0kHz +0/-5 dB
Note 15. The passband and stopband frequencies scale with fs. For example, PB = 0.185xfs (@0.04dB), SB = 0.888xfs.
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[AK4397]
DC CHARACTERISTICS (Ta=25C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.4 Low-Level Input Voltage VIL High-Level Output Voltage (Iout = -100A) VOH DVDD-0.5 Low-Level Output Voltage (Iout = 100A) VOL Input Leakage Current (Note 16) Iin -
typ -
max 0.8 0.5 10
Units V V V V A
Note 16. DFS0 and P/S pins have internal pull-up devices, nominally 100k. Therefore DFS0 pin and P/S pin are not included.
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[AK4397]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V) Parameter Symbol min Master Clock Timing Frequency fCLK 7.7 Duty Cycle dCLK 40 LRCK Frequency (Note 17) Normal Speed Mode fsn 30 Double Speed Mode fsd 54 Quad Speed Mode fsq 108 Duty Cycle Duty 45 PCM Audio Interface Timing BICK Period 1/128fn tBCK Normal Speed Mode 1/64fd tBCK Double Speed Mode 1/64fq tBCK Quad Speed Mode 30 tBCKL BICK Pulse Width Low 30 tBCKH BICK Pulse Width High 20 tBLR BICK "" to LRCK Edge (Note 18) 20 tLRB LRCK Edge to BICK "" (Note 18) 20 tSDH SDATA Hold Time 20 tSDS SDATA Setup Time DSD Audio Interface Timing 1/64fs tDCK DCLK Period 160 tDCKL DCLK Pulse Width Low 160 tDCKH DCLK Pulse Width High -20 tDDD DCLK Edge to DSDL/R (Note 19) Control Interface Timing 200 tCCK CCLK Period 80 tCCKL CCLK Pulse Width Low 80 tCCKH Pulse Width High 50 tCDS CDTI Setup Time 50 tCDH CDTI Hold Time 150 tCSW CSN High Time 50 tCSS CSN "" to CCLK "" 50 tCSH CCLK "" to CSN "" Reset Timing PDN Pulse Width (Note 20) tPD 150
typ
max 41.472 60 54 108 216 55
Units MHz % kHz kHz kHz %
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20
Note 17. When the normal/double/quad speed modes are switched, AK4397 should be reset by PDN pin or RSTN bit. Note 18. BICK rising edge must not occur at the same time as LRCK edge. Note 19. DSD data transmitting device must meet this time. Note 20. The AK4397 can be reset by bringing PDN pin "L" to "H". When the states of or DFS1-0 bits change, the AK4397 should be reset by RSTN bit.
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[AK4397]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL tBCK VIH VIL tBCKH tBCKL
LRCK
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDATA
VIH VIL
Audio Interface Timing (PCM Mode)
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[AK4397]
tDCK tDCKL tDCKH VIH VIL tDDD DSDL DSDR VIH VIL
DCLK
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = "0")
tDCK tDCKL tDCKH VIH VIL tDDD DSDL DSDR tDDD VIH VIL
DCLK
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = "0")
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
WRITE Command Input Timing
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[AK4397]
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
WRITE Data Input Timing
tPD PDN VIL
Power Down & Reset Timing
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[AK4397]
OPERATION OVERVIEW
D/A Conversion Mode
In serial mode, the AK4397 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4397 should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4397 performs for only PCM data. D/P bit Interface 0 PCM 1 DSD Table 1. PCM/DSD Mode Control
System Clock
[1] PCM Mode The external clocks, which are required to operate the AK4397, are MCLK, BICK and LRCK. MCLK should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. When external clocks are changed, the AK4397 should be reset by PDN pin or RSTN bit. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4397 is in normal operation mode (PDN pin = "H"). If these clocks are not provided, the AK4397 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4397 should be in the power-down mode (PDN pin = "L") or in the reset mode (RSTN bit = "0"). After exiting reset (PDN pin = "L" "H") at power-up etc., the AK4397 is in power-down mode until MCLK is supplied. (1) Parallel Mode (P/S pin = "H") 1. Manual Setting Mode (ACKS pin = "L") MCLK frequency is detected automatically and the sampling speed is set by DFS0 pin (Table 2). The MCLK frequency corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to "0". When DFS0 pin is changed, the AK4397 should be reset by PDN pin. Quad speed mode is not supported in this mode. DFS0 pin Sampling Rate (fs) L Normal Speed Mode 30kHz 54kHz H Double Speed Mode 54kHz 108kHz Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A 8.1920 12.2880 16.3840 24.5760 36.8640 N/A 11.2896 16.9344 22.5792 33.8688 N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 16.9344 22.5792 33.8688 N/A N/A N/A 18.4320 24.5760 36.8640 N/A N/A N/A Table 3. System Clock Example (Manual Setting Mode @Parallel Mode) BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz 5.6448MHz 6.1440MHz
128fs N/A N/A N/A 11.2896 12.2880
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2. Auto Setting Mode (ACKS pin = "H") MCLK frequency and the sampling speed are detected automatically (Table 4) and DFS0 pin is ignored. DFS0 pin should be fixed to VSS4 or DVDD. Sampling Speed Normal (fs32kHz) 512fs 768fs Normal 256fs 384fs Double 128fs 192fs Quad Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A N/A N/A 16.3840 24.5760 36.8640 N/A N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A N/A 33.8688 N/A N/A N/A N/A N/A 36.8640 N/A N/A N/A N/A N/A Table 5. System Clock Example (Auto Setting Mode @Parallel Mode) Sampling Speed Normal Double Quad MCLK 1152fs
128fs N/A N/A N/A N/A N/A 22.5792 24.5760
(2) Serial Mode (P/S pin = "L") 1. Manual Setting Mode (ACKS bit = "0") MCLK frequency is detected automatically and the sampling speed is set by DFS1-0 bits (Table 6). The MCLK frequency corresponding to each sampling speed should be provided (Table 7). The AK4397 is set to Manual Setting Mode at power-up (PDN pin = "L" "H"). When DFS1-0 bits are changed, the AK4397 should be reset by RSTN bit. DFS1 bit DFS0 bit Sampling Rate (fs) (default) 0 0 Normal Speed Mode 30kHz 54kHz 0 1 Double Speed Mode 54kHz 108kHz 1 0 Quad Speed Mode 120kHz 216kHz Table 6. Sampling Speed (Manual Setting Mode @Serial Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A 8.1920 12.2880 16.3840 24.5760 36.8640 N/A 11.2896 16.9344 22.5792 33.8688 N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 16.9344 22.5792 33.8688 N/A N/A N/A 18.4320 24.5760 36.8640 N/A N/A N/A 33.8688 N/A N/A N/A N/A N/A 36.8640 N/A N/A N/A N/A N/A Table 7. System Clock Example (Manual Setting Mode @Serial Mode) BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz 5.6448MHz 6.1440MHz 11.2896MHz 12.2880MHz
128fs N/A N/A N/A 11.2896 12.2880 22.5792 24.5760
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2. Auto Setting Mode (ACKS bit = "1") MCLK frequency and the sampling speed are detected automatically (Table 8) and DFS1-0 bits are ignored. The MCLK frequency corresponding to each sampling speed should be provided (Table 9). Sampling Speed Normal (fs32kHz) 512fs 768fs Normal 256fs 384fs Double 128fs 192fs Quad Table 8. Sampling Speed (Auto Setting Mode @Serial Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A N/A N/A 16.3840 24.5760 36.8640 N/A N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A N/A 33.8688 N/A N/A N/A N/A N/A 36.8640 N/A N/A N/A N/A N/A Table 9. System Clock Example (Auto Setting Mode @Serial Mode) Sampling Speed Normal Double Quad MCLK 1152fs
128fs N/A N/A N/A N/A N/A 22.5792 24.5760
[2] DSD Mode The external clocks, which are required to operate the AK4397, are MCLK and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit. All external clocks (MCLK, DCLK) should always be present whenever the AK4397 is in the normal operation mode (PDN pin = "H"). If these clocks are not provided, the AK4397 may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4397 should be reset by PDN pin = "L" after threse clocks are provided. If the external clocks are not present, the AK4397 should be in the power-down mode (PDN pin = "L"). After exiting reset(PDN pin = "L" "H") at power-up etc., the AK4397 is in the power-down mode until MCLK is input. DCKS bit 0 1 MCLK Frequency DCLK Frequency 512fs 64fs 768fs 64fs Table 10. System Clock (DSD Mode)
(default)
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[AK4397]
Audio Interface Format
[1] PCM Mode Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the DIF2-0 pins (Parallel mode) or DIF2-0 bits (Serial mode) as shown in Table 11. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 5 6 7 DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 Input Format BICK 0 16bit LSB justified 32fs 1 20bit LSB justified 48fs 0 24bit MSB justified 48fs 1 24bit I2S Compatible 48fs 0 24bit LSB justified 48fs 1 32bit LSB justified 64fs 0 32bit MSB justified 64fs 2 1 32bit I S Compatible 64fs Table 11. Audio Interface Format Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6 Figure 7
(default)
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK (32fs) SDATA Mode 0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
15
0
14
1
BICK (64fs) SDATA Mode 0
Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0
Lch Data
Figure 1. Mode 0 Timing
Rch Data
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK (64fs) SDATA Mode 1 SDATA Mode 4
Don't care 19:MSB, 0:LSB Don't care 23 22 21 20 19 0 Don't care 23 22 21 20 19 0 19 0 Don't care 19 0
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1, 4 Timing
Rch Data
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[AK4397]
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDATA
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23 22
Lch Data
Figure 3. Mode 2 Timing
Rch Data
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK (64fs) SDATA
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
LRCK
0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1
BICK(128fs) SDATA
0 1 2 12 13 14
31
23 24
1
31
0
0 1 2 12 13 14
31
23 24
1
31
0
0 1
BICK(64fs) SDATA
31 30 20 19 18 9 8 1 0 31 30 20 19 18 9 8 1 0 31
Lch Data 31: MSB, 0:LSB
Rch Data
Figure 5. Mode 5 Timing
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[AK4397]
LRCK
0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1
BICK(128fs) SDATA BICK(64fs) SDATA
31 30 20 19 18 9 8 1 0 31 30 20 19 18 9 8 1 0 31 31 30
0 1 2
12 11 10
12 13 14
0
23 24 31 0
31 30
1 2
12
12
11 10
13 14
0
23 24 31
31
0 1
Lch Data 31: MSB, 0:LSB
Rch Data
Figure 6. Mode 6 Timing
LRCK
0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1
BICK(128fs) SDATA
0
31
1 2
13 12 11
12 13 14
0
24 25 31 0
31
1 2
13
12
12 11
13 14
0
24 25 31 0 1
BICK(64fs) SDATA
0 31 21 20 19 9 8 2 1 0 31 21 20 19 9 8 2 1 0
Lch Data 31: MSB, 0:LSB
Rch Data
Figure 7. Mode 7 Timing
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[AK4397]
[2] DSD Mode In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can invert the polarity of DCLK.
DCLK (64fs) DCKB=1 DCLK (64fs) DCKB=0 DSDL,DSDR Normal DSDL,DSDR
Phase Modulation
D0 D0 D1 D2 D3
D1
D1
D2
D2
D3
Figure 8. DSD Mode Timing
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[AK4397]
D/A conversion mode switching timing
RSTN bit
4/fs
D/A Mode
PCM Mode 0
DSD Mode
D/A Data
PCM Data
DSD Data
Figure 9. D/A Mode Switching Timing (PCM to DSD)
RSTN bit D/A Mode
DSD Mode 4/fs
PCM Mode
D/A Data
DSD Data
PCM Data
Figure 10. D/A Mode Switching Timing (DSD to PCM) Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not recommended by SACD format book (Scarlet Book).
De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15s) and is enabled or disabled with DEM1-0 pins or DEM1-0 bits. In case of double speed and quad speed mode, the digital de-emphasis filter is always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are switched. DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF (default) 1 0 48kHz 1 1 32kHz Table 12. De-emphasis Control (Normal Speed Mode)
Output Volume
The AK4397 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to -48dB and mute. When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition time of 1 level and all 256 levels is shown in Table 13. Transition Time 1 Level 255 to 0 Normal Speed Mode 4LRCK 1020LRCK Double Speed Mode 8LRCK 2040LRCK Quad Speed Mode 16LRCK 4080LRCK Table 13. ATT Transition Time Sampling Speed
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[AK4397]
Zero Detection
The AK4397 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to "H". DZF pin of each channel immediately goes to "L" if input data of each channel is not zero after going DZF pin "H". If RSTN bit is "0", DZF pins of both channels go to "H". DZF pins of both channels go to "L" at 4 ~ 5/fs after RSTN bit returns to "1". If DZFM bit is set to "1", DZF pins of both channels go to "H" only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always "L". DZFB bit can invert the polarity of DZF pin.
Soft Mute operation
Soft mute operation is performed at digital domain. When SMUTE pin goes to "H" or SMUTE bit goes to "1", the output signal is attenuated by - during ATT_DATA x ATT transition time (Table 13) from the current ATT level. When SMUTE pin is returned to "L" or SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA x ATT transition time. If the soft mute is cancelled before attenuating - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
S M U T E pin or S M U T E bit (1) AT T _Level A ttenuation (3) (1)
-
GD (2) AOUT (4) 8192/fs GD (2)
D ZF pin
Notes: (1) ATT_DATA x ATT transition time (Table 13). For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in Normal Speed Mode. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled before attenuating - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to "H". DZF pin immediately goes to "L" if input data are not zero after going DZF pin "H". Figure 11. Soft Mute Function
System Reset
The AK4397 should be reset once by bringing PDN pin = "L" upon power-up. The analog section exits power-down mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs.
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[AK4397]
Power-Down
The AK4397 is placed in the power-down mode by bringing PDN pin "L" and the anlog outputs are floating (Hi-Z). Figure 12 shows an example of the system timing at the power-down and power-up.
PDN
Internal State D/A In (Digital)
GD
Normal Operation
Power-down
Normal Operation
"0" data
(1)
GD
D/A Out (Analog)
Clock In
MCLK, BICK, LRCK
(3) (4)
(2)
(3)
(1)
Don't care
DZFL/DZFR External MUTE
(6)
(5)
Mute ON
Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge (" ") of PDN signal. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN pin = "L"). (5) Please mute the analog output externally if the click noise (3) influences system application. The timing example is shown in this figure. (6) DZF pins are "L" in the power-down mode (PDN pin = "L"). Other: After exiting power-down mode (PDN pin: "L" "H"), AOUT pins go to VCOM voltage (AVDD/2). This time is set by a capacitor connected to VCOM pin and the internal resistor of VCOM pin. E.g. C = 10F 1 (typ) = 10F x 0.75k = 7.5ms, 5 (typ) = 37.5ms 1 (max) = 10F x 0.975k = 9.75ms, 5 (max) = 48.75ms Figure 12. Power-down/up sequence example
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[AK4397]
Reset Function
When RSTN bit = "0", the AK4397's digital section is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pins of both channels go to "H". Figure 13 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal RSTN Timing Internal State D/A In (Digital) (1) D/A Out (Analog)
Clock In
MCLK, BICK, LRCK
Normal Operation
Digital Block P d
Normal Operation
"0" data GD GD
(3)
(2) (4)
Don't care
(3)
(1)
2/fs(5)
DZFL/DZFR
Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage. (3) Click noise occurs at the edges (" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = "0"). (5) DZF pins go to "H" when the RSTN bit becomes "0", and go to "L" at 2/fs after RSTN bit becomes "1". (6) There is a delay, 3 ~ 4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2 ~ 3/fs from RSTN bit "1" to the internal RSTN bit "1". Figure 13. Reset sequence example
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[AK4397]
Register Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4397. In parallel mode, the register setting is ignored and the pin setting is ignored in serial mode. When the state of P/S pin is changed, the AK4397 should be reset by PDN pin. The serial control interface is enabled by the P/S pin = "L". In this mode, pin setting must be all "L". Internal registers may be written by 3-wire P interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit; fixed to "1"), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). The AK4397 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The writing of data becomes valid by CSN "". The clock speed of CCLK is 5MHz (max). Function Parallel mode Serial mode Auto Setting Mode O O Manual Setting Mode O O Audio Format O O De-emphasis O O SMUTE O O DSD Mode X O Zero Detection X O Slow roll-off response X O Digital Attenuator X O Table 14. Function List (O: Available, X: Not available) PDN pin = "L" resets the registers to their default values. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: READ/WRITE (Fixed to "1", Write only) A4-A0: Register Address D7-D0: Control Data Figure 14. Control I/F Timing
* The AK4397 does not support the read command. * When the AK4397 is in the power down mode (PDN pin = "L") or the MCLK is not provided, writing into the control register is inhibited. * The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is "L".
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[AK4397]
Register Map
Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 ACKS DZFE D/P ATT7 ATT7 D6 0 DZFM DSDM ATT6 ATT6 D5 0 SLOW DCKS ATT5 ATT5 D4 0 DFS1 DCKB ATT4 ATT4 D3 DIF2 DFS0 0 ATT3 ATT3 D2 DIF1 DEM1 DZFB ATT2 ATT2 D1 DIF0 DEM0 0 ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0
Notes: For addresses from 05H to 1FH, data must not be written. When PDN pin goes to "L", the registers are initialized to their default values. When RSTN bit goes to "0", the only internal timing is reset and the registers are not initialized to their default values. When the state of P/S pin is changed, the AK4397 should be reset by PDN pin.
Register Definitions
Addr Register Name 00H Control 1 Default D7 ACKS 0 D6 0 0 D5 0 0 D4 0 0 D3 DIF2 0 D2 DIF1 1 D1 DIF0 0 D0 RSTN 1
RSTN: Internal timing reset 0: Reset. All registers are not initialized. 1: Normal Operation (default) "0" resets the internal timing circuits. The register value will not be initialized. DIF2-0: Audio data interface modes (Table 11) Initial value is "010" (Mode 2: 24bit MSB justified). ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only) 0: Disable : Manual Setting Mode (default) 1: Enable : Auto Setting Mode When ACKS bit = "1", MCLK frequency and the sampling frequency are detected automatically.
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[AK4397]
Addr Register Name 01H Control 2 Default
D7 DZFE 0
D6 DZFM 0
D5 SLOW 0
D4 DFS1 0
D3 DFS0 0
D2 DEM1 0
D1 DEM0 1
D0 SMUTE 0
SMUTE: Soft Mute Enable 0: Normal Operation (default) 1: DAC outputs soft-muted. DEM1-0: De-emphasis Response (Table 12) Initial value is "01" (OFF). DFS1-0: Sampling Speed Control (Table 6) Initial value is "00" (Normal speed). When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs at that time. Slow Roll-off Filter Enable 0: Sharp roll-off filter (default) 1: Slow roll-off filter Data Zero Detect Mode 0: Channel Separated Mode (default) 1: Channel ANDed Mode If the DZFM bit is set to "1", the DZF pins of both channels go to "H" only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Data Zero Detect Enable 0: Disable (default) 1: Enable Zero detect function can be disabled by DZFE bit "0". In this case, the DZF pins of both channels are always "L".
SLOW:
DZFM:
DZFE:
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[AK4397]
Addr Register Name 02H Control 3 Default
D7 D/P 0
D6 DSDM 0
D5 DCKS 0
D4 DCKB 0
D3 0 0
D2 DZFB 0
D1 0 0
D0 0 0
DZFB: Inverting Enable of DZF 0: DZF pin goes "H" at Zero Detection (default) 1: DZF pin goes "L" at Zero Detection DCKB: Polarity of DCLK (DSD Only) 0: DSD data is output from DCLK falling edge. (default) 1: DSD data is output from DCLK rising edge. DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0: 512fs (default) 1: 768fs DSDM: DSD Input Select 0: Input pin: #5, 6, 7 (default) 1: Input pin: #12, 13, 14 When DSDM bit is changed, the AK4397 should be reset by RSTN bit. D/P: DSD/PCM Mode Select 0: PCM Mode (default) 1: DSD Mode When D/P bit is changed, the AK4397 should be reset by RSTN bit.
Addr Register Name 03H Lch ATT 04H Rch ATT Default
D7 ATT7 ATT7 1
D6 ATT6 ATT6 1
D5 ATT5 ATT5 1
D4 ATT4 ATT4 1
D3 ATT3 ATT3 1
D2 ATT2 ATT2 1
D1 ATT1 ATT1 1
D0 ATT0 ATT0 1
ATT7-0: Attenuation Level ATT = 20 log10 (ATT_DATA / 255) [dB] FFH: 0dB (default) 00H: Mute
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[AK4397]
SYSTEM DESIGN
Figure 15 show the system connection diagram. Figure 17, Figure 18 and Figure 19 show the analog output circuit examples. An evaluation board (AKD4397) is available which demonstrates the optimum layout, power supply arrangements and measurement results.
Analog5.0V
Master clock +
Digital 5.0V
10u +
0.1u
NC 37
VSS4 43
MCLK 42
AVDD 41
VSS3 40
NC 35
NC 44
NC 39
NC 38
NC 36
10u +
0.1u
1 2 3 4 5 6
DVDD PDN BICK
AOUTLP
34
Lch LPF
Lch Mute
Lch Out
AOUTLN 33
Reset & PD 64fs Audio Data fs
VSS2 32 VDDL 31 0.1u + + 0.1u 10u 10u
AK4397EQ
SDATA LRCK CSN CAD0 CCLK CDTI
VREFHL 30 VREFLL 29 NC 28 VREFLR 27 VREFHR 26 VDDR 25 0.1u
MicroController
7 8 9
10u + +
10 DIF0 11 DIF1 15 DZFR
Top View 22 AOUTRP 17 CAD1 16 DZFL 12 DIF2
VSS1 24
AOUTRN 23
0.1u
10u
14 P/S
13 NC
18 NC
19 NC
20 NC
21 NC
Rch LPF
Rch Mute
Rch Out
+
Electrolytic Capacitor Ceramic Capacitor
Notes: - Chip Address = "00". LRCK = fs, BICK = 64fs. - Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. - VSS1-4 must be connected to the same analog ground plane. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except pull-down/pull-up pins should not be left floating. Figure 15. Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial mode)
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[AK4397]
Digital Ground
Analog Ground
VSS4 43 NC 44 MCLK 42 VSS3 40 NC 36 NC 39 NC 38 NC 37 NC 35
AOUTLP 34 AOUTLN 33
1
DVDD PDN BICK SDATA LRCK CSN CAD0 CCLK CDTI
System Controller
2 3 4 5 6 7 8 9
AVDD 41
VSS2 VDDL
32 31
AK4397EQ
VREFHL 30 VREFLL NC 29 28
VREFLR 27 VREFHR 26 VDDR VSS1 22 AOUTRP 25 24
10 DFS0 11 DIF1 15 DZFR 12 DIF2 17 CAD1 16 DZFL 14 P/S 13 NC 18 NC 19 NC 20 NC 21 NC
AOUTRN 23
Figure 16. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD, respectively. AVDD, VDDL/R is supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from the point with low impedance of regulator etc. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible.
2. Voltage Reference
The differential Voltage between VREFHL/R and VREFLL/R set the analog output range. VREFHL/R pin is normally connected to AVDD and VREFLL/R pin is normally connected to VSS. VREFHL/R and VREFLL/R should be connected with a 0.1F ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor attached between VCOM and VSS eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFHL/R, VREFLL/R and VCOM pins in order to avoid unwanted coupling into the AK4397.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R - VREFLL/R = 5V) centered around VCOM. The differential outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R - VREFLL/R = 5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H(@24bit). The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Figure 17 shows an example of external LPF circuit summing the differential outputs by an op-amp. Figure 18 shows an example of differential outputs and LPF circuit example by three op-amps.
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[AK4397]
AK4397
AOUT1.5k 750 2.2n 1.5k 1.5k 1.5k 1n
+Vop
AOUT+
750 1n
-Vop
Analog Out
Figure 17. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)
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[AK4397]
Frequency Response Gain 20kHz -0.012dB 40kHz -0.083dB 80kHz -0.799dB Table 15. Filter Response of External LPF Circuit Example 1 for PCM
3.3n
+
+15 -15
100u
AOUTL- +
10u
180 3.9n
10k
330
7 3 2+ 4
0.1u
6 +
NJM5534D
10u
560 1.0n 620 560 620
0.1u
10u +
680 1.2k
0.1u
3.3n
+
1.0n NJM5534D
2- 4 + 3 7
100
6
Lch
100u
AOUTL+ +
180 3.9n
3 + 2-
10u 0.1u
+
7 6 4
0.1u 10u 10u
10k
330
NJM5534D
+
1.2k
680
0.1u
Figure 18. External LPF Circuit Example 2 for PCM 1st Stage 2nd Stage Total Cut-off Frequency 182kHz 284kHz Q 0.637 Gain +3.9dB -0.88dB +3.02dB 20kHz -0.025 -0.021 -0.046dB Frequency 40kHz -0.106 -0.085 -0.191dB Response 80kHz -0.517 -0.331 -0.848dB Table 16. Filter Response of External LPF Circuit Example 2 for PCM
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[AK4397]
It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4397 can achieve this filter response by combination of the internal filter (Table 17) and an external filter (Figure 19). Frequency Gain 20kHz -0.4dB 50kHz -2.8dB 100kHz -15.5dB Table 17. Internal Filter Response at DSD mode
2.0k 1.8k 1.0k 4.3k 270p
AOUT2.8Vpp
2200p 3300p 2.0k 1.8k 1.0k
+Vop +
AOUT+
2.8Vpp
4.3k 270p
Analog Out
6.34Vpp
-Vop
Figure 19. External 3rd order LPF Circuit Example for DSD Frequency Gain 20kHz -0.05dB 50kHz -0.51dB 100kHz -16.8dB DC gain = 1.07dB Table 18. 3rd order LPF (Figure 19) Response
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[AK4397]
PACKAGE
44pin LQFP (Unit: mm)
12.80.3 1.70max 1.40 10.0 33 34 23 0.100.10
22 12.80.3
0.8
12 44 1 0.370.08 0.20 M 010 11 0.170.05
0.60.20 0.10
Material & Lead finish
Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
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10.0
2007/05
[AK4397]
MARKING
AK4397EQ XXXXXXX
AKM
1
1) Pin #1 indication 2) AKM Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK4397 5) Audio 4 pro Logo
REVISION HISTORY
Date (YY/MM/DD) 07/05/11 Revision 00 Reason First Edition Page Contents
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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